(1) Field of the Invention
The present invention generally relates to a wireless integrated circuit having an embedded antenna on chip. More particularly, this invention relates to the design and manufacturing of the embedded antenna with air-filled trench that would improve the performance of the wireless integrated circuit while reducing cost.
(2) Description of the Prior Art
For short range, and low power transceivers, on chip antennas are preferred as they generally offer lower cost and higher reliability when compare to off chip antennas. Typically, there are two methods of transmitting electromagnetic waves (or signals) between the transmitter and the receiver: backscattering and inductive coupling. The dipole, slot and patch antennas are used in backscattering method. While spiral inductors, or loop antennas are used in inductive coupling. Inductive coupling is meant for used in short range communication, i.e. typically less than a meter. Because the field produced by the small dipole loop antenna is not a propagating wave, but rather an attenuating wave, the field strength falls off with r sup. −3, where r is the distance between the transmitting and receiving antennas. The time varying magnetic field generated from the transmitting antenna of the reader, through inductive coupling, would induce a voltage across the tag's antenna terminal. This voltage is utilized to power the passive tag device. The induced voltage is proportional to the quality factor, Q, of the antenna. In another word, the read range between the transmitting and receiving RF devices is affected by the Q of antenna and tuning circuit.
In article “The feasibility of on-chip interconnection using antennas,” in Proceedings of the IEEE/ACM Computer-Aided Design, pp. 979-984, 2005, O and his co-authors describe the design of on chip dipole antennas for inter-chip and intra-chip wireless communication. Whereas, Simons et al presents the results of spiral inductor/antenna used in a RF telemetry system for an implantable Bio-MEMS Sensor in article “RF telemetry system for an implantable Bio-MEMS sensor,” in Proc. IEEE MTT-S, pp. 1433-1436, 2004.
Any antennas fabricated on silicon substrate would have substrate effects in the millimeter wave range that would reduce the antenna efficiency. The doped silicon substrate that often found in standard CMOS and Bipolar integrated circuits is considered as lossy, due to its resistive conductivity. Time varying signal travels along metal line or polysilicon line would generate electric field and magnetic field that penetrate in the silicon substrate. The electric field would induced substrate current, whereas the magnetic field would induced eddy currents at high frequency, e.g. Giga Hertz range and beyond. More specifically, capacitive impedance, Zc, which represents the dielectric between the signal line and the substrate, is getting smaller at high frequency. Thus signal would capacitively couple to the conductive silicon substrate, inducing substrate current. With a resistive conductive substrate, this leakage substrate current would result in a resistive power loss. As for the time varying magnetic field, it induces an image current, which flows in the opposite direction, in the conductive ground substrate. So again a percentage of the signal would be loss. In addition to giving rise to power loss, according to Lenz's law, eddy currents create their own magnetic fields that is in the opposite direction of those of the signal line. This decreases the inductance of the line. For spiral inductor, this amounts to a reduction in quality factor, Q. To minimize the substrate loss, various methods: high resistivity silicon substrate, e.g. >1000 ohm.cm, removing the silicon, increasing the effective dielectric thickness between the signal lines and the silicon substrate, and implementing patterned ground shields can be used. However, each one of these methods does have its drawbacks.
High resistivity, HR, substrate, as described by Burghartz, et al, “Spiral inductors and transmission lines in silicon technology using copper damascene interconnects and low-loss substrates,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 10, pp. 1961-1968, 1997, is expensive, has much higher crystal defects, and increases latch up. However, with high resistivity silicon in the “handle” substrate (below the buried oxide) in a silicon-on-insulator, SOI, wafer, the crystal defects and latch up problems are not relevant. The HR-SOI wafers are expensive and rare, though.
U.S. Pat. No. 5,539,241 described a method to remove some or all silicon beneath the inductor by etching from the top, leaving the inductor suspended over a pit. The pit is filled with air, which is an ideal dielectric. The capacitive coupling would be much smaller. Hence the self resonance frequency of the inductor would move higher, ideally higher than the design frequency. Since the inductor is suspended, it is less mechanically stable. It is also susceptible to vibration, which causes low frequency interference, and it introduces internal stress to the surrounding area. The former phenomenon affects the circuit performance, while the latter degrades the yield of the circuit. Moreover, this method can not be applied for applications described above by Simons et al in their implantable Bio-MEMS sensor or in RFIC tag as described by Yeoh et al, “A 2.45-GHz RFID tag with on-chip antenna,” in IEEE RFIC Symp. Dig., 2006, because it would etch away the circuits which lie within the inductors.
US patent application, 20030104649, and in article “Optimization of back side micromachined CMOS inductors for RF applications,” in Proc. IEEE Int. Symp. Circuits Syst, pp. V-185-188, 2000, Ozgur et al describe another method to remove all silicon beneath the inductor. This time is by back side micromachining. Again because a very large structure is suspended, internal stress to the surrounding area is a concern. To resolve this issue, the authors deposit a stress compensation layer on the area that would be suspended before doing the back side micromachining. Using this technique, the authors claim that passive circuits occupying areas larger than 2 mm×3 mm has been micro-machined and packaged successfully. However, this method also can not be applied for applications described above by Simons et al in their implantable Bio-MEMS sensor or in RFIC tag as described by Yeoh et al, because it would etch away the circuits placing within the inductors.
Guo, et al, as described in an article “A small OCA on a 1 0.5-mm2 2.45-GHz RFID Tag—design and integration based on a CMOS-compatible manufacturing technology,” IEEE Electron Device Lett., vol. 27, pp. 96-98, 2006, neither remove the silicon underneath the inductors nor use a high resistivity silicon substrate. Instead, they deposit a very thick dielectric film, e.g. more than 15 um, in between the top metal line and the silicon substrate. The inductor is built using the top metal line. Doing this, they reduce the coupling capacitance between the inductor and the silicon substrate; thus increase the resonance frequency of the inductor. In other words, they reduce the loss due to substrate effects at the frequency they choose for the circuit to operate. The authors claim to have to overcome many challenges associated with this method. Challenges such as: wafer warps due to thick dielectric, severe polymer builds up due to deep via etch, and of filling the 15 um deep via with copper.
A patterned ground shield using poly layer, as described by Yue et al, in “On-chip spiral inductors with patterned ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, 1998, is inserted between the inductor and the silicon substrate to minimize the electric field penetration to the silicon substrate. Depending on the size of the inductors, quality factor, Q, improves only by 10% to 30%, while self-resonant frequency reduces. Q is a performance parameter of the inductor. It is defined as the ratio of the energy that is stored in the reactive portion of the component over the energy that is lost in the resistive portion of the component.
Among the above mentioned methods, removing silicon beneath the device gave the highest boost to the performance of the device, e.g. higher Q and higher resonant frequency.